The present invention relates to a semiconductor memory, and particularly to an art which is effective for a semiconductor memory having a function (nibble mode) to serially write or read data consisting of a plurality of bits.
In a dynamic RAM (random access memory), for instance, there has been proposed an access system called the nibble mode in addition to a system which accesses the data with a unit of one bit. FIG. 1 shows a timing chart of signals in the nibble mode in accordance with the conventional technique. To access the RAM, a row address strobe signal RAS and a column address signal CAS are caused to drop to the low level as shown. The column address strobe signal CAS is caused to drop several times as shown. In synchronism with the first fall of the signals RAS and CAS, the RAM takes in a pair of address signals, i.e., takes in a row address signal and a column address signal. The RAM which is capable of performing the nibble operation contains a plurality of signal holder circuits, a shift register for controlling their operation, and registers. When the address of one time is set, data consisting of four bits is given to the signal holder circuits in the RAM. The data consisting of four bits in outputted from the RAM one bit at a time in synchronism with the fall of column address strobe signal CAS as shown in the timing chart of FIG. 1.
In the dynamic RAM of this type, when an internal circuit such as a timing generator circuit is constituted by a dynamic circuit, such an internal circuit is rendered to assume a precharged state or a reset state when the column address strobe signal CAS assumes the high level, and forms various signals when the column address strobe signal CAS assumes the low level.
Here, a minimum pulse width of the column address strobe signal CAS which assumes the high level, is usually limited depending upon a system clock of an electronic system which makes use of the RAM. Therefore, when the precharging period is set depending upon the high level of the column address strobe signal CAS, the access time of the RAM tends to be delayed.